A high speed reconfigurable USART IP core with support for multi-drop networks

  • Authors:

  • Ali H. El-Mousa;Nasser Anssari;Ashraf Al-Suyyagh;Hamzah Al-Zubi

  • Affiliations:

  • Computer Engineering Department, University of Jordan, Faculty of Engineering & Technology, Amman, Jordan;Computer Engineering Department, University of Jordan, Faculty of Engineering & Technology, Amman, Jordan;Computer Engineering Department, University of Jordan, Faculty of Engineering & Technology, Amman, Jordan;Computer Engineering Department, University of Jordan, Faculty of Engineering & Technology, Amman, Jordan

  • Venue:
  • WSEAS TRANSACTIONS on SYSTEMS
  • Year:
  • 2010

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Abstract

Field Programmable Gate Arrays (FPGA) are increasingly becoming the mainstay of embedded systems due to their flexibility, speed, ease of use and reusability. At the same time, networking and data communications between the different parts of an embedded system and between different embedded systems, is becoming a necessity due to large complex projects. This paper presents the design, implementation, and testing results of a flexible and user reconfigurable Universal Synchronous Asynchronous Receive Transmit (USART) IP core suitable for use in embedded systems and Systems on Chip (SoC). The design scheme employed, allows the USART to be used in various modes of operation such as standalone and 9-bit addressable mode for multi-drop network of serial devices. It also supports high speed data rates of up to 3 Mb/s. The design utilizes Hardware Description Language (HDL) to describe the operation, ease implementation and allow cross platform utilization. The paper shows through a comprehensive testing methodology that the proposed design functions properly while consuming minimum resources from the target FPGA.