Abstract RTOS Modeling for Embedded Systems
RSP '04 Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping
Timed RTOS Modeling for Embedded System Design
RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
Enabling RTOS simulation modeling in a system level design language
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Measurement, Analysis and Modeling of RTOS System Calls Timing
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
A General Approach to High-Level Energy and Performance Estimation in SoCs
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a high-level method for rapidly and accurately estimating energy and performance overhead of Real-Time Operating Systems. Unlike most other approaches, which rely on Transaction-Level Modeling (TLM), we infer the information we need directly from executing the algorithmic specification, without needing to build any high-level architectural model. We distinguish two main components in our approach: first, an accurate one-time pre-characterization of the main RTOS functionalities in terms of energy and cycles; second, the development of an algorithm to rapidly predict the occurrences of such RTOS functionalities. Finally, we demonstrate the feasibility of our approach by comparing it against gate level for accuracy and against TLM for speed. We obtain a worst-case energy error of 12% against a mean speedup of 36X.