Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Conforming inverted data store for low power memory
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Pin: building customized program analysis tools with dynamic instrumentation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the 2008 ACM symposium on Applied computing
A low-power phase change memory based hybrid cache architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Phase-change random access memory: a scalable technology
IBM Journal of Research and Development
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Data manipulation techniques to reduce phase change memory write energy
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
PDRAM: a hybrid PRAM and DRAM main memory system
Proceedings of the 46th Annual Design Automation Conference
PCRAMsim: system-level performance, energy, and area modeling for phase-change ram
Proceedings of the 2009 International Conference on Computer-Aided Design
A frequent-value based PRAM memory architecture
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Proceedings of the 38th annual international symposium on Computer architecture
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Energy-aware writes to non-volatile main memory
HotPower '11 Proceedings of the 4th Workshop on Power-Aware Computing and Systems
Energy-aware writes to non-volatile main memory
ACM SIGOPS Operating Systems Review
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies
Proceedings of the 9th conference on Computing Frontiers
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
A dual-mode architecture for fast-switching STT-RAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Energy efficient caching for phase-change memory
MedAlg'12 Proceedings of the First Mediterranean conference on Design and Analysis of Algorithms
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Exploiting subarrays inside a bank to improve phase change memory performance
Proceedings of the Conference on Design, Automation and Test in Europe
Future memory and interconnect technologies
Proceedings of the Conference on Design, Automation and Test in Europe
WADE: Writeback-aware dynamic cache management for NVM-based main memory system
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Embedded Computing Systems (TECS)
Endurance-aware cache line management for non-volatile caches
ACM Transactions on Architecture and Code Optimization (TACO)
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Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides many benefits such as high density, non-volatility, low leakage power, and high immunity to soft error. However, its disadvantages such as high write latency, high write energy, and limited write endurance prevent it from being used as a drop-in replacement of an SRAM cache. In this paper, we study a set of techniques to design an energy- and endurance-aware PCM cache. We also modeled the timing, energy, endurance, and area of PCM caches and integrated them into a PCM cache simulator to evaluate the techniques. Experiments show that our PCM cache design can achieve 8% of energy saving and 3.8 years of lifetime compared with a baseline PCM cache having less than a hour of lifetime.