Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A hierarchial CPU scheduler for multimedia operating systems
OSDI '96 Proceedings of the second USENIX symposium on Operating systems design and implementation
APRIL: a processor architecture for multiprocessing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
In VINI veritas: realistic and controlled network experimentation
Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
NetFPGA--An Open Platform for Gigabit-Rate Network Switching and Routing
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
Internet clean-slate design: what and why?
ACM SIGCOMM Computer Communication Review
Supercharging planetlab: a high performance, multi-application, overlay network platform
Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
Comparison of the three CPU schedulers in Xen
ACM SIGMETRICS Performance Evaluation Review
A remotely accessible network processor-based router for network experimentation
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Software techniques to improve virtualized I/O performance on multi-core systems
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Building a fast, virtualized data plane with programmable hardware
Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures
PdP: parallelizing data plane in virtual network substrate
Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures
A virtual network mapping algorithm based on subgraph isomorphism detection
Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures
Analysis of network processing workloads
Journal of Systems Architecture: the EUROMICRO Journal
Simplifying data path processing in next-generation routers
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
Distributed runtime load-balancing for software routers on homogeneous many-core processors
Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow
Hi-index | 0.01 |
Network virtualization requires careful control of networking resources, including link bandwidth, router memory, and packet processing time. Isolation and fair sharing of processing resources in current high-performance packet processors occur at the granularity of entire processor cores. Scaling of network virtualization to larger numbers of parallel slices requires a more fine-grained processor sharing mechanism. Our work presents a novel approach, called Fair Multithreading (FMT), that allows hardware threads to share a processor core while ensuring isolation and weighted fair access. We present an analysis of the FMT algorithm and a prototype implementation on a NetFPGA system. Our evaluation results indicate that FMT can be implemented at speeds that are necessary to make scheduling decisions at the instruction level. We show the impact of having such fine-grained processor schedulers in substrate nodes by comparing the resource utilization of virtual network slices in our system to traditional whole-core allocations. Our simulation results show the FMT-based substrate networks can be utilized more efficiently and more virtual network requests can be accommodated. These results indicate the significant improvement in system scalability that can be gained from our fine-grained processor scheduling system.