Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient shuffle network architecture and application for WiMAX LDPC decoders
IEEE Transactions on Circuits and Systems II: Express Briefs
Digital Integrated Circuits
Iterative decoding of binary block and convolutional codes
IEEE Transactions on Information Theory
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
The capacity of low-density parity-check codes under message-passing decoding
IEEE Transactions on Information Theory
Low-density parity-check codes based on finite geometries: a rediscovery and new results
IEEE Transactions on Information Theory
A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes
Journal of Signal Processing Systems
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A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method significantly reduces the wire interconnect and decoder complexity and therefore results in fast, small, and high energy efficiency circuits. Three full-parallel decoder chips for a (2,048, 1,723) LDPC code compliant with the 10GBASE-T standard using MinSum normalized, MinSum Split-2, and MinSum Split-4 methods are designed in 65 nm, seven metal layer CMOS. The Split-4 decoder occupies 6.1 mm2, operates at 146 MHz, delivers 19.9 Gbps throughput, with 15 decoding iterations. At 0.79 V, it operates at 47 MHz, delivers 6.4 Gbps and dissipates 226 mW. Compared to MinSum normalized, the Split-4 decoder chip is 3.3 times smaller, has a clock rate and throughput 2.5 times higher, is 2.5 times more energy efficient, and has an error performance degradation of 0.55 dB with 15 iterations.