Process and Temperature Performance of a CMOS Beta-Multiplier Voltage Reference
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
Silicon-on-Sapphire Circuits and Systems
Silicon-on-Sapphire Circuits and Systems
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This paper presents the design, fabrication, and electrical measurement results from a low-noise high-performance amplifier fabricated in the 0.5 μm silicon-on-sapphire (SOS) technology. The amplifier was designed with rail-to-rail input and output swing and constant transconductance in its entire common-mode range and targets biomedical instrumentation in SOS/SOI technologies. The amplifier reports $$3\,\hbox{nV}/{\sqrt{\hbox{Hz}}}$$ of input-referred voltage noise at 10 kHz and has 0.4 mV of input-referred offset. The gain-bandwidth product of the amplifier is 12 MHz and the open-loop gain is 75 dB. The amplifier occupies 0.08 mm2 of area and consumes 1.4 mW of power.