Power and performance of read-write aware hybrid caches with non-volatile memories

Authors:
Xiaoxia Wu;Jian Li;Lixin Zhang;Evan Speight;Yuan Xie
Affiliations:
IBM Austin Research Laboratory and The Pennsylvania State University, University Park, PA;IBM Austin Research Laboratory;IBM Austin Research Laboratory;IBM Austin Research Laboratory;The Pennsylvania State University, University Park, PA
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2009

Citing 5
Cited 14

The SPLASH-2 programs: characterization and methodological considerations

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Managing Wire Delay in Large Chip-Multiprocessor Caches

Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Optimizing Replication, Communication, and Capacity Allocation in CMPs

Proceedings of the 32nd annual international symposium on Computer Architecture
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Proceedings of the 45th annual Design Automation Conference
The PARSEC benchmark suite: characterization and architectural implications

Proceedings of the 17th international conference on Parallel architectures and compilation techniques

Hybrid cache architecture with disparate memory technologies

Proceedings of the 36th annual international symposium on Computer architecture
An energy efficient cache design using spin torque transfer (STT) RAM

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Design exploration of hybrid caches with disparate memory technologies

ACM Transactions on Architecture and Code Optimization (TACO)
Enabling architectural innovations using non-volatile memory

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
A read-write aware replacement policy for phase change memory

APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
Adapting router buffers for energy efficiency

Proceedings of the Seventh COnference on emerging Networking EXperiments and Technologies
Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A dual-mode architecture for fast-switching STT-RAM

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Performance evaluation of PRAM for storage devices

Proceedings of the 2012 ACM Research in Applied Computation Symposium
Write activity reduction on non-volatile main memories for embedded chip multiprocessors

ACM Transactions on Embedded Computing Systems (TECS)
High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors

ACM Transactions on Embedded Computing Systems (TECS)
System-level impacts of persistent main memory using a search engine

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when compared with SRAM-based caches, particularly in the areas of static/dynamic power consumption, read and write access latency and cell density. In this paper, we propose to take advantage of the best characteristics that each technology has to offer through the use of read-write aware Hybrid Cache Architecture (RWHCA) designs, where a single level of cache can be partitioned into read and write regions, each of a different memory technology with disparate read and write characteristics. We explore the potential of hardware support for intra-cache data movement within RWHCA caches. Utilizing a full-system simulator that has been validated against real hardware, we demonstrate that a RWHCA design with a conservative setup can provide a geometric mean 55% power reduction and yet 5% IPC improvement over a baseline SRAM cache design across a collection of 30 workloads. Furthermore, a 2-layer 3D cache stack (3DRWHCA) of high density memory technology with the same chip footprint still gives 10% power reduction and boost performance by 16% IPC improvement over the baseline.