ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints
ACM Transactions on Embedded Computing Systems (TECS)
Enhancing multicore reliability through wear compensation in online assignment and scheduling
Proceedings of the Conference on Design, Automation and Test in Europe
Aging-aware compiler-directed VLIW assignment for GPGPU architectures
Proceedings of the 50th Annual Design Automation Conference
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In deep submicron designs of Multiprocessor Systems-on-Chip (MPSoC) architectures, uncompensated within-die process variations and aging effects will lead to an increasing uncertainty and unbalancing of expected core lifetimes. In this paper we present an adaptive workload allocation strategy for run-time compensation of variations- and aging-induced unbalanced core lifetimes by means of core activity duty cycling. The proposed techniques regulates the percentage of idle time on short-expected-life cores to meet the platform lifetime target with minimum performance degradation. Experiments have been conducted on a multiprocessor simulator of a next-generation industrial MPSoC platform for multimedia applications made of a general purpose processor and programmable accelerators.