A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
With the multiplication of mobile and wireless communication networks and standards, the physical layer of communication systems (i.e. the modem part of the system) has to be completely flexible. This assumption leads to the well known Software Defined Radio concept which enables the implementation and the deployment of different waveforms on the same platform. This concept has been widely investigated since the early 2000's mainly for processors and Sw approach but less for reconfigurable Hw or DSP implementation. This paper deals with a specific architecture and an innovative design methodology which were designed within the framework of a fully flexible high data rate Software Defined Radio wireless modem. This approach is focused on the waveform part of the system and its goal is to reach a fully flexible physical layer. In case of modem evolutions or upgrades, it enables to avoid significant rework and extra cost in term of waveform development. Moreover the association of the right architecture and the right methodology allows to master and to manage the complexity of the modem (which presents several hundred configurations available with different kind of parameters) and permits to provide the needed flexibility. The development methodology is based on a C/C++ approach which allows to manage all the parameters at a system level. The architecture coupled to this development methodology offers a high level of modularity which enables to easily modify the waveform only in replacing blocks by other blocks. The efficiency and the flexibility of the modem is then obtained by designing not a single waveform but a waveforms family.