Leading-One Prediction Scheme for Latency Improvement in Single Datapath Floating--Point Adders
ICCD '98 Proceedings of the International Conference on Computer Design
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
A wavelet visible difference predictor
IEEE Transactions on Image Processing
Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
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The richness of wavelet transformation is known in many fields. There exist different classes of wavelet filters that can be used depending on the application. In this paper, we propose an IEEE 754 floating-point lifting-based wavelet processor that can perform various forward and inverse Discrete Wavelet Transforms (DWTs) and Discrete Wavelet Packets (DWPs). Our architecture is based on processing elements that can perform either prediction or update on a continuous data stream in every two clock cycles. We also consider the normalization step that takes place at the end of the forward DWT/DWP or at the beginning of the inverse DWT/DWP. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs/DWPs. Different memory sizes and multi-level transformations are supported. For the 32-bit implementation, the estimated area of the proposed processor with 2x512 words memory and 8 PEs in a 0.18-μm process is 3.7 mm square and the estimated operating speed is 353 MHz.