An approximate timing analysis method for datapath circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Approximate timing analysis of combinational circuits under the XBD0 model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Functional timing analysis for IP characterization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing model extraction of hierarchical blocks by graph reduction
Proceedings of the 39th annual Design Automation Conference
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Timing model reduction for hierarchical timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast second-order statistical static timing analysis using parameter dimension reduction
Proceedings of the 44th annual Design Automation Conference
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Delay abstraction in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing model extraction for sequential circuits considering process variations
Proceedings of the 2009 International Conference on Computer-Aided Design
Variation-aware leakage power model extraction for system-level hierarchical power analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the correlation between delays of circuit components, timing model generation and hierarchical timing analysis face more challenges than in static timing analysis. In this paper, a novel method to generate timing models for combinational circuits considering variations is proposed. The resulting timing models have accurate input-output delays and are about 80% smaller than the original circuits. Additionally, an accurate hierarchical timing analysis method at design level using pre-characterized timing models is proposed. This method incorporates the correlation between modules by replacing independent random variables to improve timing accuracy. Experimental results show that the correlation between modules strongly affects the delay distribution of the hierarchical design and the proposed method has good accuracy compared with Monte Carlo simulation, but is faster by three orders of magnitude.