A 1.1-Gb/s 115-pJ/bit configurable MIMO detector using 0.13- µm CMOS technology

Authors:
Liang Liu;Fan Ye;Xiaojing Ma;Tong Zhang;Junyan Ren
Affiliations:
State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China;State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China;State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China;Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY;State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

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Abstract

This brief presents an efficient and configurable multiple-input-multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 × 2/3 × 3/4 × 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency, this detector also uses a candidate-sharing structure for partial Euclidean distance calculation and a two-stage sorter for survivor node selection. A test chip has been fabricated using 0.13-µm single-poly-and eight-metal (1P8M) CMOS technology with a core area of 3.9 mm2. Operating at 1.2-V supply with 137.5-MHz clock, the chip achieves 1.1-Gb/s throughput and consumes 115 pJ per bit, representing 40 % more energy efficient than state of the art in the open literature.