Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
ICS '92 Proceedings of the 6th international conference on Supercomputing
Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems
IEEE Transactions on Computers
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This paper proposes and examines some architectural features suitable for micro-vectorprocessors. Due to the I/O-pin bottleneck, micro-vectorprocessors should save the off-chip memory bandwidth by exploiting the on-chip register bandwidth instead. Those features include the vector-instruction-level multithreading and FIFO vector registers. There are three variations of multithreading:periodic, forced, and round-robin. The paper also formulates the performance of micro-vectorprocessors with such architectural features. And then, the paper evaluates the performance attainable by those micro-vectorprocessors with such architectural features. And then, the paper evaluates the performance attainable by those micro-vectorprocessors through software simulation. From the benchmark results, it is found that the vector-instruction-level multithreading and FIFO vector registers can improve the performance of the micro-vectorprocessors with the half memory bandwidth comparable to that of ones with the full memory bandwidth. Furthermore, forced multithreading is found to be tolerant to the large memory access latency. From these results, the paper concludes that the forced multithreading at the vector-instruction level is a good candidate for the architectural features suitable to micro-vectorprocessors.