Geometric algorithms for private-cache chip multiprocessors

  • Authors:
  • Deepak Ajwani;Nodari Sitchinava;Norbert Zeh

  • Affiliations:
  • MADALGO, Department of Computer Science, University of Aarhus, Denmark;MADALGO, Department of Computer Science, University of Aarhus, Denmark;Faculty of Computer Science, Dalhousie University, Halifax, Canada

  • Venue:
  • ESA'10 Proceedings of the 18th annual European conference on Algorithms: Part II
  • Year:
  • 2010

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Abstract

We study techniques for obtaining efficient algorithms for geometric problems on private-cache chip multiprocessors. We show how to obtain optimal algorithms for interval stabbing counting, 1-D range counting, weighted 2-D dominance counting, and for computing 3-D maxima, 2-D lower envelopes, and 2-D convex hulls. These results are obtained by analyzing adaptations of either the PEM merge sort algorithm or PRAM algorithms. For the second group of problems--orthogonal line segment intersection reporting, batched range reporting, and related problems--more effort is required. What distinguishes these problems from the ones in the previous group is the variable output size, which requires I/O-efficient load balancing strategies based on the contribution of the individual input elements to the output size. To obtain nearly optimal algorithms for these problems, we introduce a parallel distribution sweeping technique inspired by its sequential counterpart.