EINIC: an architecture for high bandwidth network I/O on multi-core processors

  • Authors:

  • Guangdeng Liao;Laxmi Bhuyan;Danhua Guo;Steve R. King

  • Affiliations:

  • University of California, Riverside;University of California, Riverside;University of California, Riverside;Communication Technology Lab, Intel

  • Venue:
  • Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
  • Year:
  • 2009

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Abstract

This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacity. Similar to prior work, EINIC integrates a redesigned NIC onto a CPU. However, we extend the integrated NIC (INIC) to multicore platforms and examine its behaviors with the network receiving optimization. Additionally, by exploiting NICs proximity to CPUs, we also design an I/O-aware last level shared cache (LLC). Our I/O-aware design allows us to split the cache into an I/O cache and a general cache in a flexible way. It ameliorates cache interferences between network and non-network data. Our simulation results show that EINIC not only attacks the mismatch, but also ameliorates the cache interference.