Memory event clocks

  • Authors:

  • James Jerson Ortiz;Axel Legay;Pierre-Yves Schobbens

  • Affiliations:

  • Computer Science Faculty, University of Namur;INRIA, IRISA, Rennes and Institut Montefiore, University of Liège;Computer Science Faculty, University of Namur

  • Venue:
  • FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
  • Year:
  • 2010

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Abstract

We introduce logics and automata based on memory event clocks. A memory clock is not really reset: instead, a new clock is created, while the old one is still accessible by indexing. We can thus constrain not only the time since the last reset (which was the main limitation in event clocks), but also since previous resets. When we introduce these clocks in the linear temporal logic of the reals, we create Recursive Memory Event Clocks Temporal Logic (RMECTL). It turns out to have the same expressiveness as the Temporal Logic with Counting (TLC) of Hirshfeld and Rabinovich. We then examine automata with recursive memory event clocks (RMECA). Recursive event clocks are reset by simpler RMECA, hence the name "recursive". In contrast, we show that for RMECA, memory clocks do not add expressiveness, but only concision. The original RECA define thus a fully decidable, robust and expressive level of real-time expressiveness.