Design of a scalable and programmable sound synthesizer

  • Authors:
  • Tae-Hwan Kim;Young-Joo Lee;In-Cheol Park

  • Affiliations:
  • Division of Electrical Engineering, the School of Electrical Engineering and Computer Science, Korea Advanced Institution of Science and Technology, Daejeon, Korea;Division of Electrical Engineering, the School of Electrical Engineering and Computer Science, Korea Advanced Institution of Science and Technology, Daejeon, Korea;Division of Electrical Engineering, the School of Electrical Engineering and Computer Science, Korea Advanced Institution of Science and Technology, Daejeon, Korea

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2010

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Abstract

Sound synthesis employed in many multimedia systems is a useful method to generate the sound of musical instruments. Although it has a long history of development, a few researches have been devoted to deriving efficient VLSI architectures. In this paper, we analyze the inherent dataflow of sound synthesis methods and propose a programmable VLSI architecture suitable for a scalable sound synthesizer. The sound quality and the level of polyphony can be enhanced only by increasing the operating speed and enlarging the memory. A fully integrated sound synthesis system is implemented as a prototype to verify the proposed architecture. The prototype chip fabricated in a 0.18-µm CMOS process occupies 1.5 mm × 1.5 mm, and can synthesize a 64-polyphonic sound in real time. The power consumption ranges from 2.05 to 13.8 mW depending on the level of polyphony and the sound quality.