RF microelectronics
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This paper discusses the challenges in ultrawideband pulse radio transceiver design and proposes an architecture operating between 3.1 and 10.6 GHz to address them. The 7.5-GHz band is subdivided into multiple channels of 500 MHz each to relax the requirements for pulse generation, transceiver synchronization, and group-delay flatness. The pulse bases for these channels are stored in digital memories and are used for pulse generation on the transmit side and correlation on the receive side. The transceiver can operate in combination with a fast interferer detector that quickly sweeps through the channels to determine which channels are occupied by large interferers and are thus unsuitable for communication. The all-digital pulse bases allow the transceiver to quickly switch between different channels to avoid interferers without needing multiple or, alternatively, broadband fast-settling phase-locked loops. The frequency plan allows the most critical 802.11 interferers to be pushed to higher frequencies during the first block downconversion where they are attenuated by the low-pass filters of the receiver. The wideband intermediate-frequency correlation architecture significantly relaxes the speed requirement of the digital circuit and the local memories. Several signal-processing techniques to eliminate sampling images in the transmitter as well as spurious image responses in the receiver are also presented. The proposed architecture is digitally intensive and, hence, can take advantage of technology scaling.