ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies

Authors:
Shuqing Cao;Jung-Hoon Chun;Stephen G. Beebe;Robert W. Dutton
Affiliations:
Integrated Circuits Laboratory, Department of Electrical Engineering, Stanford University, Stanford, CA;Department of Semiconductor Systems Engineering, Sungkyunkwan University, Suwon, Korea;GlobalFoundries, Sunnyvale, CA;Integrated Circuits Laboratory, Department of Electrical Engineering, Stanford University, Stanford, CA
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
Year:
2010

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Abstract

Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamp devices. Recent progress on ESD protection design for both high-speed digital I/O and radiofrequency (RF) circuits are presented. Topological trade-offs are compared. High speed circuit protection techniques such as the T-coil based ESD design are reviewed in detail. Package- and wafer-level charged device model (CDM) correlation issues are discussed. I/O, ESD devices, and metal interconnect effects are examined using very fast transmission line pulses (VF-TLP) and TLP.