Improved usability and performance of SMT solvers for debugging specifications

Authors:
David R. Cok
Affiliations:
Eastman Kodak Company, Rochester, NY, USA
Venue:
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on VSTTE 2008
Year:
2010

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Abstract

It is now common to construct an extended static checker or software verification system using an SMT theorem prover as the underlying logical verifier. SMT provers have improved significantly in performance over the last several years. However, their usability as a component of software checking and verification systems still has gaps. This paper describes investigations in two areas: the reporting of counterexample information and the testing of vacuity, both of which are important to realistic use of such tools for typical software development. The use of solvers in verification is more effective if the solvers support minimal unsatisfiable cores and incremental construction, evolution and querying of satisfying assignments; current solvers only partially support these capabilities.