Hardware-efficient fair queueing architectures for high-speed networks

  • Authors:
  • Jennifer L. Rexford;Albert G. Greenberg;Flavio G. Bonomi

  • Affiliations:
  • Department of EECS, University of Michigan, Ann Arbor, MI;Network Services Research, AT&T Bell Laboratories, Murray Hill, NJ;ZeitNet Inc., Santa Clara and AT&T Platform Organization, AT&T network Systems, Red Bank, NJ

  • Venue:
  • INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
  • Year:
  • 1996

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Abstract

In emerging communication networks, a single link may carry traffic for thousands of connections with different traffic parameters and quality-of-service requirements. High-speed links, coupled with small packet/cell sizes, require efficient switch architectvres that can handle cell arrivals and departures every few microseconds, or faster. This paper presents a collection of self-clocked fair queueing (SCFQ) architectures amenable to efficient hardware implementatnon in network switches. Exact and approximate implementations of SCFQ efficiently handle a moderate range of connectaon bandwidth parameters, while hierarchical arbitration schemes scale to a large range of throughput requirements. Simulation experiments demonstrate that these architectures divide link bandwidth fairly on a small time scale, preserving connection bandwidth and burstiness properties.