Making proportional bandwidth guarantees in IEEE 802.11e enhanced distributed channel access

  • Authors:
  • Ye Ge;Jennifer C. Hou

  • Affiliations:
  • Dept. of Electrical Engineering, Ohio State University;Department of Computer Science, University of Illinois at Urbana-Champaign

  • Venue:
  • MILCOM'06 Proceedings of the 2006 IEEE conference on Military communications
  • Year:
  • 2006

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Abstract

In this paper, we derive, based on the analytical model developed by Cali et al., a multi-class model to study how to adaptively tune parameters in IEEE 802.11e EDCA and support service differentiation in WLANs. Through analytical modeling, we demonstrate that by assigning appropriate different attempt probabilities (or contention window sizes) to stations of different classes, it is feasible to provide (proportional) service differentiation and achieve pre-specified targeted throughput ratios among different classes, while at the same time, maximizing the total system capacity. We also extend the derived theoretical model to analyze the role of AIFS and TXOP values on service differentiation perceived by different traffic classes. We show that, to achieve QoS guarantees (i.e. throughput differentiation) and high channel utilization, it may not be desirable to allow tuning of multiple parameters (e.g., both the contention window sizes and the AIFS values). Instead, the design dimension should be kept small by turning only one set of parameters, while keeping the other two sets of parameters for all the access categories fixed (i.e., setting the AIFS values of all access categories to 2, which is equivalent to AIFS=DIFS). We also elaborate on how to on-line measure parameters needed for calculating the best value of the contention window size. Both the analytical models and the proposed approaches for practically incorporating theoretical findings into IEEE 802.11e EDCA are validated through detailed ns-2 simulations and empirical experimentation on a Linux-based MADWifi driver for wireless LAN devices with the Atheros chipset.