IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
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A novel architecture is presented to optimize the noise performance and the power consumption of the transconductance `gm' boosted common-gate (CG) ultrawideband (UWB) low-noise amplifier (LNA), operating in the 3---5 GHz range, by employing current reuse technique. This proposed CG LNA utilizes a common source (CS) amplifier as the gm-boosting stage and the bias current is shared between the gm-boosting stage and the CG amplifying stage. The LNA circuit also utilizes the short channel conductance gds in conjunction with an LC T-network to further reduce the noise figure (NF). The proposed LNA architecture has been fabricated using the 130 nm IBM CMOS process. The LNA achieved input return loss (S11) of 驴8 to 驴10 dB, and, output return loss (S22) of 驴12 to 驴14 dB, respectively. The LNA exhibits almost flat forward voltage gain (S21) of 13 dB, and reverse isolation (S12) of 驴62 to 驴49 dB, with a NF ranging between 3.8 and 4.6 dB. The measurements indicate an input-referred third order intercept point (IIP3) of 驴6.1 dBm and an input-referred 1-dB compression point (ICP1dB) of 驴15.4 dBm. The complete chip draws 4 mW of DC power from a 1.2 V supply.