Typestate: A programming language concept for enhancing software reliability
IEEE Transactions on Software Engineering
ACM Transactions on Computer Systems (TOCS)
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Towards the generation of efficient code from verified programs
Towards the generation of efficient code from verified programs
An Overview of the Runtime Verification Tool Java PathExplorer
Formal Methods in System Design
Experimental Evaluation of Verification and Validation Tools on Martian Rover Software
Formal Methods in System Design
Comparing the expressive power of access control models
Proceedings of the 11th ACM conference on Computer and communications security
Partition Analysis: A Method Combining Testing and Verification
IEEE Transactions on Software Engineering
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This paper presents initial research on unification of methods for verification and validation (V&V)of software systems. The synergism among methods for V&V are described. The requirements for a unification are defined. The initial steps of a case study of application of the unified approach to V&V is sketched including definition of the problem domain, the approach and some details of a property specification language. An undergraduate course introducing the unified approach to V&V is described. The relationship of this research to other efforts toward unification of V&V are discussed.