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ACM Computing Surveys (CSUR)
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Communications of the ACM
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SC '97 Proceedings of the 1997 ACM/IEEE conference on Supercomputing
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IEEE Micro
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VLDB '98 Proceedings of the 24rd International Conference on Very Large Data Bases
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VLDB '90 Proceedings of the 16th International Conference on Very Large Data Bases
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VLDB '92 Proceedings of the 18th International Conference on Very Large Data Bases
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PNPM '97 Proceedings of the 6th International Workshop on Petri Nets and Performance Models
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IEEE Transactions on Parallel and Distributed Systems
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Workstation clusters equipped with high performance interconnect having programmable network processors facilitate interesting opportunities to enhance the performance of parallel application run on them. In this paper, we propose schemes where certain application level processing in parallel database query execution is performed on the network processor. We evaluate the performance of TPC-H queries executing on a high end cluster where all tuple processing is done on the host processor, using a timed Petri net model, and find that tuple processing costs on the host processor dominate the execution time. These results are validated using a small cluster. We therefore propose 4 schemes where certain tuple processing activity is offloaded to the network processor. The first 2 schemes offload the tuple splitting activity - computation to identify the node on which to process the tuples, resulting in an execution time speedup of 1.09 relative to the base scheme, but with I/O bus becoming the bottleneck resource. In the 3rd scheme in addition to offloading tuple processing activity, the disk and network interface are combined to avoid the I/O bus bottleneck, which results in speedups upto 1.16, but with high host processor utilization. Our 4th scheme where the network processor also performs a part of join operation along with the host processor, gives a speedup of 1.47 along with balanced system resource utilizations. Further we observe that the proposed schemes perform equally well even in a scaled architecture i.e., when the number of processors is increased from 2 to 64.