Dynamic configuration steering for a reconfigurable superscalar processor

Authors:
Nick A. Mould;Brian F. Veale;Monte P. Tull;John K. Antonio
Affiliations:
University of Oklahoma, School of Electrical and Computer Engineering, Norman, OK;University of Oklahoma, School of Computer Science, Norman, OK;University of Oklahoma, School of Electrical and Computer Engineering, Norman, OK;University of Oklahoma, School of Computer Science, Norman, OK
Venue:
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Year:
2006

Citing 5
Cited 0

Microarchitecture support for dynamic scheduling of acyclic task graphs

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures

IEEE Transactions on Parallel and Distributed Systems
Benchmarking the Task Graph Scheduling Algorithms

IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Configuration Steering for a Reconfigurable Superscalar Processor

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
MiBench: A free, commercially representative embedded benchmark suite

WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous work that used steering vectors to guide the selection of functional units to be loaded into the processor. Dependencies among instructions in the instruction buffer are analyzed to enable a new scoring method. The dynamic vector technique is shown to reduce the amount of reconfiguration required while preserving execution resources. Simulation results reveal that, given enough configurable space, the configuration of the processor approaches a stable state.