A 32-Bit SoPC Implementation of a P5
ISCC '03 Proceedings of the Eighth IEEE International Symposium on Computers and Communications
A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA
AICT-SAPIR-ELETE '05 Proceedings of the Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop
Parallel realization of the ATM cell header CRC
Computer Communications
Generic framing procedure (GFP): the catalyst for efficient data over transport
IEEE Communications Magazine
Data transport applications using GFP
IEEE Communications Magazine
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This paper presents the design and study of reconfigurable architectures for two data-link layer frame delineation techniques used for ATM and GFP. The architectures are targeted to Altera Stratix II FPGA technology and are investigated in terms of performance and area. This work addresses the potential for incorporating programmability into custom purpose architectures that could enable the same processing hardware to be used for processing multiple protocols.