X-Network: An area-efficient and high-performance on-chip wormhole interconnect network
Microprocessors & Microsystems
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Packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future chip multiprocessors and complex Systems on Chip (SoCs). However, the quest for highperformance networks has led to very area-consuming and complicated routers with little return in performance. This paper presents X-Network, a low-area and high-performance wormhole-switching NoC that is built on a novel PE (Processing Element)-router organization. In X-Network, each router is shared by four PEs and each general PE has access to four directly-connected routers in addition to NEWS (North, East, West, South) connections between neighboring PEs. By sharing routers among PEs, the network reduces the average hop count for packets thereby reducing the latency and improving the throughput of the network. Our design not only reduces the total number of routers for a given number of PEs, but also offers much more routing flexibility compared to existing mesh-based solutions. Any routing algorithm can be used in X-Network after incorporating our router selection functions. Extensive simulation results using both synthetic workloads and the SPLASH-2 applications show that X-Network can reduce average network latency by 51% for a system with 64 PEs. The network saturation point is extended by up to approximately 100% using a fully-adaptive routing algorithm.