Memory-efficient TCP reassembly using FPGA
Proceedings of the Second Symposium on Information and Communication Technology
A query-matching mechanism over out-of-order event stream in IOT
International Journal of Ad Hoc and Ubiquitous Computing
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There is a growing interest in designing high-speed network devices to perform packet processing at stream layer. However, variety kinds of out-of- sequence packets in real traffic will make trouble for hardware-based TCP reassembly system which is less flexible for exceptional processing. In this paper, we present a detailed analysis of behavior characteristic of out-of-sequence packets in real backbone traffic and propose a hardware-based solution for TCP reassembly based on the results of analysis. This solution could reassemble a TCP stream with concurrent multi discontinuous out-of-order data segments and provide a robust buffer management strategy for out-of-order data. We have also assessed the memory size and bandwidth required for reassembling real 10G traffic. The simulation result shows that the system can process over 99% of the 10G backbone traffic using reasonable storage resources. A FPGA-based prototype is also implemented for evaluation.