DVFS-control techniques for dense linear algebra operations on multi-core processors
Computer Science - Research and Development
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Given an initial schedule of a parallel program represented by a directed acyclic graph (DAG) and an energy constraint, the question arises how to effectively determine what nodes (tasks) can be penalized (slowed down) through the use of dynamic voltage scaling. The resulting re-schedule length with a strict energy budget should have a minimum amount of expansion compared to the original schedule achieved with full energy. We propose three static schemes that aim to achieve this goal. Each scheme encompasses submitting a schedule to either a conceptual “stretch” (starting tasks with a maximum voltage supplied to all cores followed by methodical voltage reductions) or “compress” (starting tasks with a minimum voltage supplied to all cores followed by methodical voltage boosts). The complexity arises due to the inter-dependence of tasks. We propose methods that efficiently make such findings by analyzing the DAG and determining the “impact factor” of a node in the graph for the purpose of guiding the schedule toward the desired goal. The comparison between the stretch-alone and compress-alone based algorithms leads to a third algorithm that employs schedule “compression,” but reschedules all cores following each successive voltage adjustment. Detailed simulation experiments demonstrate the effect of various task and processor parameters on the performance of the proposed algorithms.