Energy and thermal aware buffer cache replacement algorithm

  • Authors:

  • Jianhui Yue;Yifeng Zhu;Zhao Cai;Lin Lin

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Maine, Orono, USA;Department of Electrical and Computer Engineering, University of Maine, Orono, USA;Department of Electrical and Computer Engineering, University of Maine, Orono, USA;Department of Electrical and Computer Engineering, University of Maine, Orono, USA

  • Venue:
  • MSST '10 Proceedings of the 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST)
  • Year:
  • 2010

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Abstract

Power consumption is an increasingly impressing concern for data servers as it directly affects running costs and system reliability. Prior studies have shown most memory space on data servers are used for buffer caching and thus cache replacement becomes critical. Temporally concentrating memory accesses to a smaller set of memory chips increases the chances of free riding through DMA overlapping and also enlarges the opportunities for other ranks to power down. This paper proposes a power and thermal-aware buffer cache replacement algorithm. It conjectures that the memory rank that holds the most amount of cold blocks are very likely to be accessed in the near future. Choosing the victim block from this rank can help reduce the number of memory ranks that are active simultaneously. We use three real-world I/O server traces, including TPC-C, LM-TBF and MSN-BEFS to evaluate our algorithm. Experimental results show that our algorithm can save up to 27% energy than LRU and reduce the temperature of memory up to 5.45掳C with little or no performance degradation.