Explicit Communication and Synchronization in SARC

Authors:
Manolis Katevenis;Vassilis Papaefstathiou;Stamatis Kavadias;Dionisios Pnevmatikatos;Federico Silla;Dimitrios Nikolopoulos
Affiliations:
FORTH-ICS, Heraklion;FORTH-ICS, Heraklion;FORTH-ICS, Heraklion;FORTH-ICS, Heraklion;Universidad Politecnica de Valencia, Valencia;FORTH-ICS, Heraklion
Venue:
IEEE Micro
Year:
2010

Citing 0
Cited 2

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Abstract

A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency.