ACM Transactions on Computer Systems (TOCS)
Flexible Control of Parallelism in a Multiprocessor PC Router
Proceedings of the General Track: 2002 USENIX Annual Technical Conference
RouteBricks: exploiting parallelism to scale software routers
Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
Leveraging parallelism for multi-dimensional packetclassification on software routers
Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems
PacketShader: a GPU-accelerated software router
Proceedings of the ACM SIGCOMM 2010 conference
RouteBricks: enabling general purpose network infrastructure
ACM SIGOPS Operating Systems Review
Toward predictable performance in software packet-processing platforms
NSDI'12 Proceedings of the 9th USENIX conference on Networked Systems Design and Implementation
Design and implementation of a consolidated middlebox architecture
NSDI'12 Proceedings of the 9th USENIX conference on Networked Systems Design and Implementation
The power of batching in the Click modular router
Proceedings of the Asia-Pacific Workshop on Systems
The power of batching in the click modular router
APSys'12 Proceedings of the Third ACM SIGOPS Asia-Pacific conference on Systems
NetBump: user-extensible active queue management with bumps on the wire
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
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Software routers promise to enable the fast deployment of new, sophisticated kinds of packet processing without the need to buy and deploy expensive new equipment. The challenge is offering such programmability while at the same time achieving a competitive level of performance. Recent work has demonstrated that software routers are capable of high performance, but only for conventional, simple workloads (like packet forwarding and IP routing) and, even that, after careful manual calibration. In contrast, we are interested in achieving high performance in the context of a software router running multiple sophisticated packet-processing applications. In particular: first, we identify the main factors that affect packet-processing performance on a modern multicore general-purpose server---cache misses, cache contention, load-balancing across processing cores; then, we formulate an optimization problem that takes as input a particular server architecture and a packet processing flow, and determines how to parallelize the router's functionality across the available cores so as to maximize its throughput.