Property specification patterns for finite-state verification
FMSP '98 Proceedings of the second workshop on Formal methods in software practice
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
From States to Transitions: Improving Translation of LTL Formulae to Büchi Automata
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Fair Simulation Relations, Parity Games, and State Space Reduction for Büchi Automata
ICALP '01 Proceedings of the 28th International Colloquium on Automata, Languages and Programming,
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Fast LTL to Büchi Automata Translation
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
SPOT: An Extensible Model Checking Library Using Transition-Based Generalized Büchi Automata
MASCOTS '04 Proceedings of the The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications
Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications
Proceedings of the 14th international SPIN conference on Model checking software
LTL translation improvements in spot
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
LTL to büchi automata translation: fast and more deterministic
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
LTL translation improvements in Spot 1.0
International Journal of Critical Computer-Based Systems
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Explicit-state model checkers like SPIN, which verify systems against properties stated in linear-time temporal logic (LTL), rely on efficient LTL-to-Büchi translators. A difficult design decision in such constructions is to trade time spent on minimizing the Büchi automaton versus time spent on model checking against an unnecessarily large automaton. Standard reduction methods like simulation quotienting are fast but often miss optimization opportunities. We propose a new technique that achieves significant further reductions when more time can be invested in the minimization of the automaton. The additional effort is often justified, for example, when the properties are known in advance, or when the same property is used in multiple model checking runs. We use a modified SAT solver to perform bounded language inclusion checks on partial solutions. SAT solving allows us to prune large parts of the search space for smaller automata already in the early solving stages. The bound allows us to fine-tune the algorithm to run in limited time. Our experimental results show that, on standard LTL-to-Büchi benchmarks, our prototype implementation achieves a significant further size reduction on automata obtained by the best currently available LTL-to-Büchi translators.