Integration of Equality Reasoning into the Disconnection Calculus
TABLEAUX '02 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
Encodings of Bounded LTL Model Checking in Effectively Propositional Logic
CADE-21 Proceedings of the 21st international conference on Automated Deduction: Automated Deduction
Logical Engineering with Instance-Based Methods
CADE-21 Proceedings of the 21st international conference on Automated Deduction: Automated Deduction
Deciding Effectively Propositional Logic Using DPLL and Substitution Sets
IJCAR '08 Proceedings of the 4th international joint conference on Automated Reasoning
Instantiation-Based Automated Reasoning: From Theory to Practice
CADE-22 Proceedings of the 22nd International Conference on Automated Deduction
Testing strong equivalence of datalog programs – implementation and examples
LPNMR'05 Proceedings of the 8th international conference on Logic Programming and Nonmonotonic Reasoning
The model evolution calculus with equality
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
iProver-Eq: an instantiation-based theorem prover with equality
IJCAR'10 Proceedings of the 5th international conference on Automated Reasoning
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The Inst-Gen-Eq method is an instantiation-based calculus which is complete for first-order clause logic modulo equality. Its distinctive feature is that it combines first-order reasoning with efficient ground satisfiability checking which is delegated in a modular way to any state-of-the-art ground SMT solver. The first-order reasoning modulo equality employs a superposition-style calculus which generates the instances needed by the ground solver to refine a model of a ground abstraction or to witness unsatisfiability. In this paper we present and compare different labelling mechanisms in the unit superposition calculus that facilitates finding the necessary instances. We demonstrate and evaluate how different label structures such as sets, AND/OR trees and OBDDs affect the interplay between the proof procedure and blocking mechanisms for redundancy elimination.