A graph covering algorithm for a coarse grain reconfigurable system
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Efficient Place and Route for Pipeline Reconfigurable Architectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
The software radio architecture
IEEE Communications Magazine
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We have developed an original reconfigurable processor LSI for software radio systems for consumer products. The die size of the LSI is 5.65 mm by 5.65 mm. The processor is based on ALU array architecture and has original limitations on connections of ALUs. The circuit size is small because of the limitations. It achieves high processing performance by processing multiple threads simultaneously. We have developed a prototype of a broadcasting receiver with the LSIs. The prototype has realised the real-time reception of three kinds of broadcasts by changing software using a maximum of two LSIs. We also have estimated a power consumption of the LSI and have confirmed that power consumption can be reduced by approximately 55% of that of the LSI. By doing so, we have advanced a realisation of software radio for consumer products.