Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface

• Authors: Christoforos Kachris;George Nikiforos;Stamatis Kavadias;Vassilis Papaefstathiou;Manolis Katevenis
• Venue: RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
• Year: 2010

Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. A multicore FPGA platform with cache-integrated network interfaces (NIs) is presented, appropriate for scalable multicores, that combine the best of two worlds –the flexibility of caches (using implicit communication) and the efficiency of scratchpad memories (using explicit communication): on-chip SRAM is configurable shared among caching, scratchpad, and virtualized NI functions. The proposed system has been implemented in a four-core FPGA. Special hardware primitives (counter, queues) are used for the the communication and synchronization of the cores that are most suitable in network processing applications. The paper presents the performance evaluation of the proposed system in the domain of network processing. Two representatives benchmarks are used, one for header processing and one for payload processing. The system is evaluated in terms of performance and the communication overhead is measured. Furthermore, two approaches for the communication of the processors are evaluated and compared, common queue and distributed queues.