Performance and Energy Implications of Many-Core Caches for Throughput Computing

Authors:
Christopher Hughes;Changkyu Kim;Yen-Kuang Chen
Affiliations:
Intel, Santa Clara;Intel, Santa Clara;Intel Corporation , Santa Clara
Venue:
IEEE Micro
Year:
2010

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Abstract

Processors that target throughput computing often have many cores, which stresses the cache hierarchy. Logically centralized, shared data storage is needed for many-core chips to provide high cache throughput for heavily read-write shared lines. Techniques to reduce on-die and off-die traffic have a dramatic energy benefit for many-core chips.