Communication and Concurrency
Automata For Modeling Real-Time Systems
ICALP '90 Proceedings of the 17th International Colloquium on Automata, Languages and Programming
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Symbolic Model Checking of Real-Time Systems
TIME '01 Proceedings of the Eighth International Symposium on Temporal Representation and Reasoning (TIME'01)
Software/Hardware Engineering with the Parallel Object-Oriented Specification Language
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
From POOSL to UPPAAL: Transformation and Quantitative Analysis
ACSD '10 Proceedings of the 2010 10th International Conference on Application of Concurrency to System Design
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Packet switched networks are widely used for interconnecting distributed computing platforms. RapidIO (Rapid Input/Output) is an industry standard for packet switched networks to interconnect multiple processor boards. Key performance metrics for these platforms include average-case and worst-case packet transfer latencies. We focus on verifying such quantitative properties for a RapidIO based multiprocessor platform that executes a motion control application. A performance model is available in the Parallel Object-Oriented Specification Language (POOSL) that allows for simulation based estimation results. It is however required to determine the exact worst-case latency as the application is time-critical. A model checking approach has been proposed in our previous work which transforms the POOSL model into an UPPAAL model. However, such an approach only works for a fairly small system. We extend the transformation approach with various heuristics to reduce the underlying state space, thereby providing an effective approximation approach that scales to industrial problems of a reasonable complexity.