A compressive sensing algorithm for many-core architectures

Authors:
A. Borghi;J. Darbon;S. Peyronnet;T. F. Chan;S. Osher
Affiliations:
LRI, INRIA, Université Paris Sud, Orsay;CMLA, ENS Cachan, CNRS, PRES UniverSud, France;LRI, INRIA, Université Paris Sud, Orsay;Hong Kong University of Science and Technology, Hong Kong;UCLA Mathematics Department
Venue:
ISVC'10 Proceedings of the 6th international conference on Advances in visual computing - Volume Part II
Year:
2010

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Abstract

This paper describes a parallel algorithm for solving the l1- compressive sensing problem. Its design takes advantage of shared memory, vectorized, parallel and many-core microprocessors such as Graphics Processing Units (GPUs) and standard vectorized multi-core processors (e.g. quad-core CPUs). Experiments are conducted on these architectures, showing evidence of the efficiency of our approach.