An efficient retargetable microcode generator

  • Authors:

  • M. Balakrishnan;P. C P Bhatt;B. B. Madan

  • Affiliations:

  • Computing and Information Science Department, University of Guelph,Guelph, Ontario,Canada,N1G2W1;Department of Computer Science and Engineering, Indian Institute of Technology,Delhi, New Delhi,India,110016;Department of Computer Science and Engineering, Indian Institute of Technology,Delhi, New Delhi,India,110016

  • Venue:
  • MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
  • Year:
  • 1986

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Abstract

This paper presents a microcode generator, which accepts a source program (algorithm) and a target description (microarchitecture) as input and generates microcode to implement the algorithm on the defined microarchitecture. The target description is similar to the outputs produced by datapath synthesis phase in hardware design packages. Thus, it can be incorporated to synthesise a microprogrammed control.The microcode generator is based on an algorithm which preserves retargetability without sacrificing on design time. This is achieved by implementing the generator in two phases: in the first phase, a set of 'feasible' register transfer operations (called base-set) is generated from the microarchitecture description. In the second phase, translation is carried out by simply searching and matching the source program statements with the base-set.