IEEE Transactions on Computers
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Fault-tolerant computer system design
Fault-tolerant computer system design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Power consumption of parallel spread spectrum correlator architectures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Spread Spectrum PN Code Acquisition Using Hybrid Correlator Architectures
Wireless Personal Communications: An International Journal
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Energy Aware Computing through Probabilistic Switching: A Study of Limits
IEEE Transactions on Computers
Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
Novel low-overhead operand isolation techniques for low-power datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
IEEE Communications Magazine
Computation as estimation: a general framework for robustness and energy efficiency in SoCs
IEEE Transactions on Signal Processing
What is stochastic computation?
ACM SIGDA Newsletter
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In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (PDet) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in (PDet) by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.