Single chip digital down converter architecture

Authors:
Mike Petrowski;David B. Chester;W. Ronald Young
Affiliations:
Harris Semiconductor, Melbourne, FL;Harris Corporation, Harris Semiconductor, Melbourne, FL;Harris Semiconductor, Melbourne, FL
Venue:
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
Year:
1993

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Abstract

The architecture and algorithmic advancements of the Harris HSP50016 digital down converter (DDC) are described. The DDC is a fully programmable single chip down converter architected to perform intermediate frequency (IF) to baseband processing for communications signal processing. The operation and specification of each major function within the DDC is described and justification for key specifications is given. The end-to-end performance of the DDC is shown and the methodology used for measuring the performance is explained.