Parallel morphological image processing with an opto-electronic VLSI array processor

  • Authors:

  • Wai-Chi Fang;Timothy Shaw;Jeffrey Yu;Brian Lau;Yi-Chun Lin

  • Affiliations:

  • Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA

  • Venue:
  • ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
  • Year:
  • 1993

Quantified Score

Hi-index 0.00

Visualization

Abstract

A parallel morphological image processor (MIP) has been developed onto a full-custom optoelectronic VLSI design by combining a 2-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. The optical I/O array processor performs morphological functions on the opto-detected binary image with a programmable structuring element of any size. A specific language called MIPL is defined for parallel morphological image processing and fully supported by the MIP hardware. An 8×8 array processor prototype chip has been designed in 1.6 mm × 1.6 mm silicon area using the MOSIS 2-µm CMOS process.