Area efficient VLSI architectures for Huffman coding

  • Authors:

  • Heonchul Park;Viktor K. Prasanna

  • Affiliations:

  • Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA;Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA

  • Venue:
  • ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
  • Year:
  • 1993

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Abstract

In this paper, we present simple and area efficient VLSI architectures for Huffman coding, an industrial standard proposed by MPEG, JPEG, and others. We use a memory of size O(n log n) to store a Huffman code tree, where n is the number of symbols. It requires few simple arithmetic operations on the chip for realtime encoding and decoding. Based on our scheme, we show a design for 8-bit symbols. The proposed design requires 256 × 9 and 64 × 18-bit memory modules to process 8-bit symbols. The chip occupies a silicon area of 3.5 × 3.5mm2 using 1.2 micron CMOSN standard library cells. Compared with, known parallel implementation [7] which requires upto 65536 PES, the proposed architecture leads to a single PE design.