Dynamic Partitioning of Shared Cache Memory
The Journal of Supercomputing
A Case for MLP-Aware Cache Replacement
Proceedings of the 33rd annual international symposium on Computer Architecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Adaptive insertion policies for high performance caching
Proceedings of the 34th annual international symposium on Computer architecture
Cooperative cache partitioning for chip multiprocessors
Proceedings of the 21st annual international conference on Supercomputing
Adaptive insertion policies for managing shared caches
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Proceedings of the 36th annual international symposium on Computer architecture
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To improve performance and fairness of the LLC shared among the multiple cores, the recent Promotion/Insertion Pseudo-Partitioning (PIPP) that combines dynamic insertion and promotion into the cache management policy. Compared with PPIP, in this work we propose a new Homologous Promotion Insertion Policy (HPIP) which can determine the insertion position when a new core situation occurs and balance the cache resource allocation simultaneously. HPIP depends on the existing cache structure and require negligible change overhead. In addition, we analyze Dynamic Insertion Policy (DIP) and maintain that the sampling sets selection for Set Dueling Monitors (SDM) should be according to a processor's cores number rather than the running applications. Finally, our experiments with multi-programmed workloads for 2-core, 4-core CMPs based on M5 simulator show that the performance of HPIP approximate to PPIP and its adaptive capability is enhanced.