FPGA prototyping of neuro-adaptive decoder

Authors:
Cecilia Sandoval Ruiz
Affiliations:
Institute Mathematical and Applied Computing, University of Carabobo and Telecommunication Department, UNEFA, Carretera Nacional Maracay-Mariara, Edo-Aragua, Venezuela
Venue:
CIMMACS '10 Proceedings of the 9th WSEAS international conference on computational intelligence, man-machine systems and cybernetics
Year:
2010

Citing 3
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Abstract

In this paper we present a design of a neuro-adaptive decoder with Very High Speed Integrated Circuit Hardware Description Lenguage (VHDL) based on Multi-Layer Perceptron Neural Network (MLP), FPGAs have been used for ANN implementation due to accessibility. For the design to choice case studie Reed Solomon RS(7,4) code, the methodology correspond to modular design of Artificial Neural Network, for the configuration of network elements in VHDL was used Xilinx ISE 11 tool. In the results presents structure of ANN, report of training, VHDL codes of ANN Decoder, the Register Transfer Level (RTL) schematic and synthesis report.