Dynamic Logic
Universally Quantified Interval Constraints
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Incremental Closure of Free Variable Tableaux
IJCAR '01 Proceedings of the First International Joint Conference on Automated Reasoning
Simplify: a theorem prover for program checking
Journal of the ACM (JACM)
Soundness and completeness warnings in ESC/Java2
Proceedings of the 2006 conference on Specification and verification of component-based systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Efficient E-Matching for SMT Solvers
CADE-21 Proceedings of the 21st international conference on Automated Deduction: Automated Deduction
Satisfiability solving for software verification
International Journal on Software Tools for Technology Transfer (STTT)
Complete Instantiation for Quantified Formulas in Satisfiabiliby Modulo Theories
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Solving quantified verification conditions using satisfiability modulo theories
Annals of Mathematics and Artificial Intelligence
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Proving programs incorrect using a sequent calculus for Java dynamic logic
TAP'07 Proceedings of the 1st international conference on Tests and proofs
Challenges in satisfiability modulo theories
RTA'07 Proceedings of the 18th international conference on Term rewriting and applications
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Verification of object-oriented software: The KeY approach
Verification of object-oriented software: The KeY approach
TAP'10 Proceedings of the 4th international conference on Tests and proofs
Test data generation for programs with quantified first-order logic specifications
ICTSS'10 Proceedings of the 22nd IFIP WG 6.1 international conference on Testing software and systems
Sequential, parallel, and quantified updates of first-order structures
LPAR'06 Proceedings of the 13th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
What's decidable about arrays?
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
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The generation of models, i.e. interpretations, that satisfy first-order logic (FOL) formulas is an important problem in different application domains, such as, e.g., formal software verification, testing, and artificial intelligence. Satisfiability modulo theory (SMT) solvers are the state-of-the-art techniques for handling this problem. A major bottleneck is, however, the handling of quantified formulas. Our contribution is a model generation technique for quantified formulas that is powered by a verification technique. The model generation technique can be used either stand-alone for model generation, or as a precomputation step for SMT solvers to eliminate quantifiers. Quantifier elimination in this sense is sound for showing satisfiability but not for refutational or validity proofs. A prototype of this technique is implemented.