Fault modeling and characteristics of SRAM-based FPGAs (abstract only)

  • Authors:

  • Naifeng Jing;Ju-Yueh Lee;Chun Zhang;Jiarong Tong;Zhigang Mao;Lei He

  • Affiliations:

  • Shanghai Jiao Tong University, Shanghai, China;University of California, Los Angeles, Los Angeles, CA, USA;Fudan University, Shanghai, China;Fudan University, Shanghai, China;Shanghai Jiao Tong University, Shanghai, China;University of California, Los Angeles, Los Angeles, CA, USA

  • Venue:
  • Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
  • Year:
  • 2011

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Abstract

The reliability of SRAM-based Field Programmable Gate Array (FPGA) is susceptible to Single Event Upset (SEU) fault. To investigate the fault impact, particular the fault in interconnects on FPGA functionality, this paper proposes a SEU fault analysis framework by evaluating the fault with a unified metric. This metric, termed as criticality, quantifies the sensitivity of FPGA functional failure to the SEU fault on logical and interconnect configuration bits. Considering the post layout information, our framework can characterize the SEU fault with respect to different FPGA architectures and CAD algorithms, such that the sensitivity of FPGA functional failure can be investigated in detail during design phase. The experiment result quantitatively shows that the configuration bits in interconnects dominate those in LUTs, several times both in bit number and criticality contribution. The ratio of their criticalities is even higher when LUT input size increases from 4 to 6. The higher criticality of interconnects than their LUT counterpart is due to their natural sensitivity to functional failure instead of their majority of bits. In addition, it is also shown that, among the three common types of switch boxes, the Subset switch box is less fault tolerant than Wilton and Universal.