A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video

Authors:
Cheng-An Chien;Yao-Chang Yang;Hsiu-Cheng Chang;Jia-Wei Chen;Cheng-Yen Chang;Jiun-In Guo;Jinn-Shyan Wang;Ching-Hwa Cheng
Affiliations:
National Chung-Cheng University, Chia-Yi, Taiwan;National Chung-Cheng University, Chia-Yi, Taiwan;National Chung-Cheng University, Chia-Yi, Taiwan;National Chung-Cheng University, Chia-Yi, Taiwan;National Chung-Cheng University, Chia-Yi, Taiwan;National Chung-Cheng University, Chia-Yi, Taiwan;National Chung-Cheng University, Chia-Yi, Taiwan;Feng-Chia University, Tai-Chung, Taiwan
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

Citing 1
Cited 0

Overview of the Scalable Video Coding Extension of the H.264/AVC Standard

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.